India is a rapidly growing economy and a fast growth is expected in the industrial and transportation infrastructure. Naturally, the energy requirements are set to ramp up at high values and the question of supply becomes a very important one. There is an urgent need to think about developing those technologies which will enable us to utilize the vast resources that are available in the country. This is because it is clear that conventional resources cannot fulfill our long-term needs, even when they are stretched to their maximum practicable limits. Currently fission reactors contribute about 4% of our present capacity, but they are expected to play an important role in the coming decades by increasing their share.
 
Our strength and independence lies in our own resources. Utilizing the thorium resources in the long run is a part of DAE’s vision. Nuclear fusion now enjoys an important place in this vision. Apart from fusion-power, there are important applications of energetic neutrons from fusion reaction in the interim period. We must therefore develop this technology for our own energy security and multifarious applications.
 
 
Nuclear fusion
 
It is the process, which has kept the sun and other stars burning brilliantly for billions of years. In the quest for star-fire in the laboratory, one tries to duplicate in the laboratory, the same nuclear fusion reaction albeit with different reactants: that is between the two nuclei of hydrogen isotopes (deuterium and tritium).
 
D + T → He++ (3.5MeV) + n (14.1MeV).
 
Thermonuclear fusion occurs when the D and T ions in hot and dense plasma undergo a chance collision in which the nuclei come so close together that the fusion reaction takes place. This can happen only at high enough energies so that the matter is in plasma state. In a reactor, neutrons come out as fast projectiles but can be trapped in a blanket surrounding the reactor core, producing heat, which can be used to generate steam and produce electricity using conventional turbines.
 
The motivation for developing fusion as an energy source lies in its possible large scale contribution in the second-half of this century, with a virtually inexhaustible fuel supply, attractive safety characteristics and an acceptable environmental impact.
 
The excellent energy multiplication factor (∼500, per reaction) allows one to have a net gain in power, in spite of the fact that only about 0.1% of the fuel in the reactor actually gets consumed. The neutron can be trapped by a ‘blanket’ surrounding the plasma core and made to react with a lithium containing material in order to re-generate the ‘lost’ triton. With the D available from the ample sea-water and T-generated within the reactor-blanket, an interesting fuel-economics results, especially when one notes that barely a gram of gaseous fuel is within the reactor at any given time (e.g., the input and exhaust approximately same at 30 milligrams/sec of D or T for a 1000 m3 volume). For a full-power-year burn, one needs about 30 kg of tritium for consumption, but when the complete fuel-cycle is considered the required inventory on-site is much reduced as fuel extraction and re-injection time is of the order of days. The key features of the fusion power are: wide availability (including lithium ores, in fact a very interesting geological distribution when compared to oil , less volume of fuel to handle, less complexity, significantly low radioactive waste, passive safety (the reaction stops automatically when the temperature is lowered) and practically inexhaustible fuel supply. These features are so tremendously attractive that they remain a strong driver for exploring fusion energy source in spite of its well-known criticism over expected delay in realization.
 
There were many different configuration proposed to confine the plasma effectively and tried world-wide. The most successful amongst them is the so called ‘tokamak’ (a magnetic bottle to hold the hot and dense plasma). It is a torus shaped vessel in which the toroidalmagnetic field (BT) is produced by the toroidal-field coils and a poloidal Magnetic field (Bθ ) by a superposition of poloidal-field coils as well as a current (Ip) flowing within the plasma itself.
 
In thermonuclear fusion research using magnetic confinement, tokamak is the most promising candidate to demonstrate fusion as achievable energy source. A tokamak (Toroidalnaya Kamera Magnitnaya Katushka or "Toroidal Vessel with Magnetic Coils”) is a toroidal device which uses a strong toroidal magnetic field, to confine high temperature plasma within the torus for a sufficiently long time. Final goal of the tokamak research is to reach fusion of deuterium and tritium nuclei for production of electricity.
 
Like any other science/technology, plasma science/fusion technology is not without its spin-off benefits. A very large number of people around the world have been working on plasma and its applications for almost 40 years. In terms of returns to society, the vital role of plasma-based technologies in etching processes and revolutionizing the field of electronic circuit miniaturization and enabling compact high-speed computing is well-known. It is already a multi-billion dollar industry. A great many of plasma applications flow from the fact that it is a very reactive medium, due to high particle energies and sensitive to electromagnetic fields. Processing of mineral ores, improving hardness of surfaces for improved wear-and-tear and bio-medical waste incineration are some of the fast growing industries.
 
There are three important applications of fusion in the fission area. First, some of the longlived nuclear waste from fission reactors can be treated with an intense neutron source to improve its management by transmuting it to short-lived waste. Second, it will be possible to convert fertile material like thorium to uranium (U233) and third, it is possible to conceive a sub-critical fission reactor (thorium) which uses fusion neutrons as a driver. These potential applications in the interim period can justify investment in fusion technology development.

Fusion research in India
 
During early 1970s theoretical and experimental studies in plasma physics to understand space plasma phenomena was initiated in the Physical Research Laboratory (PRL), Ahmedabad. In the early days the experiments were conducted for understanding a variety of nonlinear plasma phenomena with linear and toroidal devices. The theory activities spanned fields like turbulence, transport, basic plasma physics, nonlinear dynamics, astrophysical plasmas, quark-gluon plasma, etc. In 1982, the Department of Science and Technology identified the magnetic confinement fusion research as a high priority thrust area and initiated ‘Plasma Physics Program’ (PPP) in PRL. In PPP, emphasis grew on study of phenomena in toroidal devices and developing insights into the confinement and transport phenomena. The BETA device (Basic Experiments on Toroidal Assembly) was designed and built.
 
In 1986, PPP transformed into a major program, when it separated as the DST-funded Institute for Plasma Research (IPR) at Gandhinagar. A major achievement of IPR has been the indigenous design, fabrication and erection of the tokamak ADITYA.  ADITYA was commissioned in September 1989 and has already generated scientific results on turbulent processes in tokamaks, which are of considerable interest to the international community. It earned a name for itself in discovering ‘intermittency’ or ‘blobby’ nature of complex transport mechanism and underpinning short-term coherent structure formation in otherwise turbulent plasma. In addition, a number of fusion technologies such as large volume UHV (ultra-high vacuum) systems, large pulsed electromagnets, pulsed power systems, sophisticated plasma diagnostics, plasma surface-cleaning methods, RF (radio-frequency) heating systems in the MHz range have been indigenously developed. Apart from ADITYA, India also has a smaller tokamak, purchased as a complete system from TOSHIBA Ltd. of Japan which has been set-up at the Saha Institute of Nuclear Physics, Kolkata (SINP). It has produced very interesting results of interest to turbulence and dynamo mechanism.

Next major program at the Institute for Plasma Research has been to construct a Steady State Superconducting Tokamak (SST-1) by mix of import and indigenous development. The aim of this experiment is to (i) generate the essential database particularly for understanding the interaction between the plasma and the wall of tokamak in long pulse steady-state discharges and (ii) develop various fusion relevant technologies. SST-1 has a major radius of 1.1 m and a minor radius of 0.2 m, elongation of 1.7 and triangularity of 0.4–0.7, toroidal field of 3 T and a plasma current of 220 kA. In this machine, a typical plasma discharge will be of 1000 s. Auxiliary heating and current drive will be carried out using Lower Hybrid Current Drive mechanism (GHz waves) and heating by Ion Cyclotron Resonance Heating (ICRH) and Neutral Beam Injection (NBI). The auxilliary heating systems are necessary as the conventional ohmic heating is not efficient at high temperatures. Most of the subsystems of SST-1 have been fabricated, assembled and individually tested before final assembly. The basic machine itself has now been re-assembled after a setback on the magnet systems during its first commissioning. Cool-down trials of the toroidal field magnets have been successful and integrated tests of all systems are completed.
 
It is worth noting that the above programs have led to a significant knowledge and capability addition to various Indian industries.
 
India joined the ITER consortium on 5-Dec-2005 with an aim to accelerate the gap-closure between indigenous technology and that which is required to build a DEMO reactor. Indigenous development of fusion technologies was started in XI Plan for magnet, divertor and cryopumping areas. In collaboration with Atomic Fuels Division, IPR has achieved the milestone of making the superconducting strands, making a cable-in-conduit conductor and making a magnet from the same. The point to note is that during the SST-1 tokamak (1997–98) we had bought the conductor from Hitachi. Now it is possible to make it ourselves. In the area of divertor, we have been able to make small scale samples of tungsten-mounted on copper blocks (collaboration with NFTDC Hyderabad) and subject them to extreme heat fluxes (5MW/m2. Here, we will be able to break free from the limitation of 0.5MW/m2 as is present in SST-1. In the area of cryopumping, we have been able to complete the design and R&D on materials and start making of prototype cryopumps. Notable developments have been made on heating and current-drive technologies in terms of increasing their performance parameters. Collaborative development of new systems like ion-source for negative neutral beam using cesium has also been started.
 
About ITER
                                                                                                                         
ITER is the world’s first fusion reactor experiment which will lead to a first ever exploration of physics of burning plasmas, charting a new territory in the science and technology of fusion. It will usher a strong development of enabling technologies for ensuring success of future fusion-power reactors. The seven Parties which are contributing to ITER are China, EU, India, Japan, Korea, Russia and the US. ITER-India is the domestic agency for executing India’s share of in-kind procurements for the ITER Project, being hosted by EU (5/11th share of construction).
India’s share is 1/11th (like other five partners). The knowledge generated from the experiments will be shared equally by all the ITER-members.

Aiming for DEMO
 
The construction and operation of the SST-1 machine will give enough insight into plasma wall interactions under long pulse conditions. Many key technology areas such as superconducting magnets, control systems, heating and current drive systems, and cryogenics will also be tested in the process. However, there will still be considerable knowledge and technological gap to be covered before electricity producing fusion reactor can be built. IPR’s vision is to build a demonstration fusion power reactor (DEMO) which produces electricity. Considering the estimated efficiency of power conversion from fusion to thermal (0.5) and from thermal to electrical (0.4), a fusion reactor of 1 GWf needs to be targeted initially so that a net electrical output of about 200 MWe. Improvements are very likely in the meanwhile in conversion efficiency.
 
R&D plans for technology gaps
 
After the operation and experimentation on SST-1 machine, and contribution to the construction of ITER, focus will be on the following:
 
1. Continue to participate in ITER into the operation phase and contribute to achieve energy yield factor of 10. The scientific outcome will be included in the design of the next reactor, which will produce continuous fusion power. 

2. Continue research on SST-1 on finer aspects of control and physics issues. 
 
3. Development of technologies: 
​

• Large superconducting magnets (GJ class), Cryogenics (plants of tens of kW capacity at LHe temperature).

 

• Non-inductive Current Drive (5 GHz) and Heating systems (tens of MW), Neutral Beam Heating system (beams of order MV).

 

• Large vacuum components, Fusion Fuel Cycle and Tritium systems.

 

• Materials and technologies for blanket and diverter, irradiation and other test facility development.

 

• Diagnostics and reactor control systems.

 

• Safety systems, remote handling and hot cell.

​We will post more about Adhithya , SST1 & ITER in the following articles.

Introduction
 
General purpose on-chip processors have become ubiquitous today. These processors range from extremely small and low power micro-controllers (used in motor controls, robotic platforms, home-appliances, etc.) to hefty and high-performance multi-core processors (used in servers and supercomputers). However, the growth of modern domain-specific languages (like Caffe, Tensorflow, etc.) and the need for more specialized features like machine-learning, enhanced security, etc. has forced the industry to look beyond general purpose solutions and towards mass-customization. While a large number of companies today can develop custom ASICs (Application Specific Integrated Chips) and license specific silicon blocks from chip-vendors to develop a customized SoCs (System on Chips), at the heart of every design is the processor and the associated hardware. To serve modern workloads better, these processors also need to be customized, upgraded, re-designed and augmented suitably. This requires that vendors/consumers have access to relevant processor variants and the flexibility to make modifications and ship them at an endurable cost. 

Today, a fair share of the processor market is dominated by just a few giants like Intel, ARM, AMD, etc. Each of these companies have an impressive IP portfolio of processors catering to various market trends. Almost all of the IP offerings of these companies fall under a licensing model which varies significantly. For example, Intel licenses its ISA only to limited users like AMD. ARM on the other hand offers a broad of range of licenses from ISA to architectural licenses. Apart from just license fees, these companies also charge royalties on devices using their IPs. Having sustained a successful IP model, today some of these licenses can go upto 1-10\$ Million in addition to strict NDAs which may restrict the user from making any proprietary changes or even publishing relevant numbers. All these aspects of the licensing model, while benefiting the respective companies, has made is difficult for consumers to develop truly customized solutions for modern day workloads. Some of these customizations cater to too low a market sector for the giants themselves to invest in, thereby prohibiting growth and novelty. 

In essence, the closed-source IP model in the processor community is proving to be a hindrance to build scalable solutions. A similar struggle in the software industry against closed-source IP led to the rise of the open-source Linux kernel in the 1990s. Since then the software community has seen a plethora of open-source software and tool-chains which have been adopted by industry and academia both. The hardware community however, hasn't seen such a revolution yet and is probably in dire need of the same. An open-source processor eco-system will not only boost customization but also allow bright minds of the industry and academia to collaborate and provide a stable and viable framework competent enough with modern-day products. SHAKTI, an open-source initiative by IIT-Madras (Indian Institute of Technology Madras) is primarily aimed at building such open-source processor development eco-systems which can equip the community with enough ammunition to build custom and industrial grade processors without the hassle of licensing, NDAs, royalties or any other sort of restrictions. 

The SHAKTI Program

The SHAKTI Processor Program was started as an academic initiative back in 2014 by the RISE group at IIT-Madras. Realizing the limitations of the processor industry mentioned above, the initiative aimed at not only creating open-source industrial grade processors but also building associated components of a bigger eco-system - like interconnect fabrics, scalable verification platforms, peripheral IPs, etc. - which enables rapid adoption of the processors. Some of the major highlights of the program which make it a viable option for adoption are:

• Source code of all the components of the SHAKTI eco-system is open under the 3 part BSD license. This means a user could freely use, modify and circulate the source code without having to sign any NDAs, licenses or even notify the authors as long as the license header file remains. The SHAKTI program itself will not assert any patents and thereby removes the burden of paying royalties as well.

• The processors of the SHAKTI eco-system are build using the open-source RISC-V ISA. RISC-V has been designed for modularity and extensions, thereby perfectly fitting the prologue of "customization". The ISA also comes with a complete software stack, including compilers, operating systems, and debuggers, which are open source and thus also modifiable. Since the ISA does not dictate micro-architectural features, the software and hardware can be maintained by two complete different entities and yet be compatible. This allows for great re-usability and sharing of code-base across the community.

• The SHAKTI processors and the front-end (RTL) designs are developed using the open-source High Level Synthesis (HLS) language: Bluespec System Verilog (BSV). BSV equips the user to develop extremely modular and parameterized modules with defined interfaces. This feature facilitates the user to focus and modify only the designs of interest without having to break the rest of the flow. Today there exists a free bsv-parser which the community can use to develop open/proprietary compilers for BSV.

• Academia now has access to a real world working prototypes of processors which they can play with for free. This enables them to depart from the world of "simulators" and "emulation models" and try out their research and ideas in practice. They are no longer tied down by strict NDAs on publishing and can thereby participate more actively in shaping the future of the processor industry.

• A typical process of acquiring ISA or architectural licenses from companies like ARM can vary anywhere between 6-12 months. This increases the time-to market for the consumers. SHAKTI, can immensely reduce this time by avoiding such formalities and providing a powerful modular framework allowing small tech start-ups to only modify components of interest rather than building a solution from scratch.

• With minds from all over the community pouring in ideas and solutions, SHAKTI has the potential to become a state-of-the-art offering quickly

• An open-source eco-system such as SHAKTI promotes a mix-and-match environment where users can plug-in different open-source or proprietary IPs and innovate on new ideas and projects.

• Being completely open-source, it is close-to-impossible for external entities to add back-doors and black-boxes. This is of particular interest to strategic sectors of countries like India, which today depend on black-box solutions provided by industries which are headquartered in foreign countries.

• SHAKTI can also enable the software community drastically. Fearing strong patent lawsuits, software developers who own licensed HW IPs for development are forced to release only binaries rather source code and also provide minimal documentation. This leaves the software Libre community in dangling state, spending months and even years \emph{"picking up pieces"}.

 
In addition to the above arguments, a combination of the open-source processor eco-systems such as SHAKTI and a fabrication entity like TSMC, which is offering upto 100 small tests chips on its latest technology node for only 30,000\$, can virtually enable any project with real-chips for their final validation at drastically low costs and time.

Source Code 
​
A majority of the front-end design of SHAKTI is done using Bluespec System Verilog. The bluespec compiler can generate a cycle-accurate C model, which in simulation is 8-10x faster than state-of-the-art verilog simulators. This drastically speeds up verification of designs. Additionally, the BSV generated verilog is not only well structured and human readable/maintainable but is also 100% synthesizable, enabling users to start prototyping on FPGAs from day-1. It also perevents classes of design errors like race-conditions and type errors from happeneing, thereby obviating the need for verification in these areas. This represents a paradigm change in CPU architecture design flow. A large part of the verification tools and auxiliary components are developed using python

​Members of the Shakti Processor Team : G. S. Madhusudan, Vishvesh Sundararaman, Arjun Menon, Vinod Ganesan, Shankar Raman, Neel Gala, Deepa N Sarma, Gopinathan M., Rahul Bodduna

Ecosystem ComponentsSHAKTI has envisioned a family of processors as part of its road-map, catering to different segments of the market. They have been broadly categorized into "Base Processors", "Multi-Core Processors" and "Experimental Processors".

Base Processors 
E Class 
This is our embedded class processor, built around a 3-stage in-order core. It is aimed at low-power and low compute applications and is capable of running basic RTOSs like FreeRTOS, Zephyr and eChronos. Market segments include: smart-cards, IoT sensors, motor-controls and robotic platforms

C Class
The C Class is a controller class of processors, aimed at mid-range application workloads. The core is a highly optmized, 5-stage in-order design with MMU support and capability to run operating systems linux and seL4. These processors are targeted at compute/control applications in the 500 MHz - 1.5 Ghz range. The C-class will support the full RISC-V ISA(Instruction Set Architecture). The C Class is also the basis for our Tagged-ISA and Fault tolerant cores.

I Class
Equipped with performance oriented features like out-of-order execution, multi-threading, aggressive branch prediction, non-blocking caches and deep pipeline stages. the I-Class processors are targeted at the compute , mobile, storage and networking the mobile and networking segments. Target operating range - 1.5-2.5 Ghz. 

Multi-Core ProcessorsThis category consists of multi-core variants with auxiliary computational units meant to serve high-performance compute requirements

M Class             
           This is a mobile class processor with a maximum of 8 cores, the cores being a combination of C and I class cores. Tile-Link is used as the cache-coherent interconnect used along along with transaction adapters/bridges to AXI4/AHB to connect to fast and/or slow peripherals. The tilelink topology is customizable to allow optimations for various power/performance targets. In typical configurations, it is expected that a core complex of 2 or 4 cores will share an L2 cache. L3 caches are optional and are typically expected to be used in desktop type applications.

S Class
The S-Class is aimed at Workstation and Enterprise serever workloads. The base core is an enhanced version of the I-class, with quad-issue and multi-threading support. A tile-link based cache coherent mesh fabric is the intercoonect of choice. Cores are expected to use dedicated L2 caches and segmented L3 caches. A maximum core count of 32 will be supported. External interconnect is expected to be Gen-Z and we are considering supporting multi-socket cache coherenecy based on a MOESIF style protocol running on top of Gen-Z.

H Class
SoC configuration aimed at highly parallel enterprise ,HPC and analytics workloads. The cores can be a combination of C or I class, single thread performance driving the core choice. Optional L4 caches and an optimized memory hierarchy is key to achieveing a high memory bandwidth. The architecture thrust is on accelerators, VPU and AI/ML and an mesh SoC fabric optimized for up to 128 cores with multiple accelerators per core. Close integration with an external Gen-Z fabric is a key part of the design, as is support for storage class memory. This aspect of the design is crucial since I/O and memory bandwidth is often the bottleneck for these classes of processors.
 
Experimental ProcessorsThese categories of cores are experimental in nature and will include variants of the base-class processors modified to meet specific criteria

T Class
A varinat of the C-Class that explores tag based ISAs for object level security. We plan to support corase and fine grain tags. Coarse grain tags will be used to realize micro-VM like functionality. to mitigate software attacks like buffer-overflow.

F Class
T-Class processors are fault tolerant versions of the base-processors. Features include redundant compute blocks (like DMR and TMR), temporal redundancy modules to detect permanent faults, lock-step core configurations, fault localization circuits, ECC for critical memory blcoks and redundant bus fabrics. These are also a key component of our ASIL-D solutions and autonmous vehicle compute blocks.


According to Sources, Shakti is already going into production with the first design in the control system of an experimental civilian nuclear reactor[prototype Fast Breeder reactor].

Source :- https://shaktiproject.bitbucket.io/  [Official Website of Shakti Program]